Video is captured at speeds of up to 6.25 Gigabits/Second (Gb/S). Simultaneously, control commands and triggers can be sent to the camera 20 Mb/S (with a trigger accuracy of +/- 2 nanoseconds). Up to 13 W of power can also supplied to the camera. All this happens over a single piece of industry standard 75 Ohm coaxial cable.
Multiple CXP links can be aggregated to support higher data rates (e.g. four links provide 25 Gb/S of data).
The CXP standard opens the door to applications where cable cost, routing requirements and long distances have prevented the move to high resolution, high speed digital cameras. In many cases, existing coaxial infrastructure can be repurposed for CXP with very low installation costs.
The Cyton-CXP is based on BitFlow's brand new PCIe Gen 2.0 platform. To develop the Cyton platform, we first started with a clean slate, and asked ourselves, "what does a next generation frame grabber need?" For sure, it needs a Gen 2.0 PCIe x8 back end for the ultimate high speed access to host memory. It also needs a sophisticated DMA engine to handle the demands of new camera interface standards. New standards demand flexibility. For example, CXP cameras will soon be able to put out streams of random sized ROIs, something our previous generation DMA engine was not capable of. Finally, we know based on years of experience of making frame grabbers, that it needs flexible and powerful I/O, triggering and routing. The CoaXPress front end is based on our Karbon-CXP, but upgraded and ready for the coming changes in the CXP standards. The Cyton platform is the foundation for today's and tomorrows frame grabbers, be it CoaXPress, Camera Link, or whatever new standards emerge from the Machine Vision industry.
Efficient support for variable sized images with fast context switches between frames
Per frame control of acquisition properties (AOI specifically)
Hardware control of image sequencing
Enhanced debug capabilities
Efficient support for on-demand buffer allocation (Genicam model)
Gracefully recover from dropped packets (either on the input side or the DMA side)